Starting with PCI Express® 1.0 at 2.5 GT/s, each successive generation of the standard has doubled the data rate of the previous generation. The current generation, PCIe® 5.0, operates at 32 GT/s. PCIe 6.0 will continue this doubling, although in a unique way—it moves from the nonreturn-to-zero (NRZ) signaling of the previous generations to four-level pulse amplitude modulation (PAM4) signaling.

Why PAM4?

Whereas NRZ transmits one bit per unit interval (UI), PAM4 transfers two bits per UI, allowing the data rate to double without doubling the channel bandwidth. PAM4 signals exhibit several characteristics that differ from NRZ signals. An NRZ signal is a two-level signal that produces one eye per UI (Figure 1, left). By contrast, the four-level PAM4 signal produces three eyes (Figure 1, right). The peak-to-peak voltage level for a PCIe 5.0 32-GT/s NRZ signal is the same as that for a PCIe 6.0 64-GT/s PAM4 signal, but the three eyes of a PAM4 signal have a reduced eye height and eye width, which requires tighter noise and jitter tolerances, presenting one of the challenges of moving to PAM4 signaling.

Figure 1. NRZ signal with one eye per UI, left, and PAM4 signal with three eyes, right.

Because the multilevel PAM4 signal is more susceptible to noise than the NRZ signal, the jitter seen at a PCI 6.0 device’s receiver must be kept low to ensure so that the receiver can determine whether an individual UI represents a 0, 1, 2 or 3. In addition, for a PAM4 signal, a 0 to 1 transition has a much slower slew rate compared to a 0 to 3 transition. Because of this slew-rate difference, jitter measurements on a multi-transition PAM4 signal, with its four voltage levels, require a more complex measurement algorithm compared to algorithms needed for an NRZ signal.

How PCIe 6.0 Addresses Tighter Tolerances

The PCIe standard utilizes two specifications to define electrical testing requirements in the course of its development cycle: the Base specification and the Card Electromechanical (CEM) specification. Used in the first part of the development cycle, the Base specification defines the fundamental device behavior from the physical layer through the protocol layers. At the physical layer, it describes characteristics like voltage swing, timing and jitter measured at a chip's transmitter and receiver pins.

Figure 2 shows the electrical Base testing methodologies for both PCIe 5.0 and 6.0. For transmitter EQ, Rx calibration and BER testing, the measurement methods across both generations remain the same. For the critical transmitter jitter measurements, PCIe 6.0 adds PAM4 methods while retaining some NRZ measurements. In addition, both PCIe 5.0 and 6.0 transmitter voltage measurements use a compliance pattern, but the compliance pattern is different for PCIe 5.0, which uses NRZ signal modulation, than for PCIe 6.0, which uses PAM4 signal modulation. Finally, signal to noise and distortion ratio (SNDR) and ratio of level mismatch (RLM), highlighted in green, are new measurements introduced with PCIe 6.0.

Figure 2. Electrical Base test measurements for both PCIe 5.0 and PCIe 6.0.

The CEM specification defines the interface where two devices from different vendors can interoperate. At the physical layer, the CEM specification defines the same characteristics such as voltage swing, timing and jitter measured in the Base specification, but these characteristics are measured at the CEM connector rather than at the chip pin. The jitter, transmitter EQ preset, SNDR and RLM measurements for the CEM specification use the same methods as for PCIe 6.0 Base testing shown in Figure 2.

Figure 3 shows the additional measurements required for CEM testing—notably LEQ, PLL and Reference Clock measurements—with some PCIe 6.0 CEM measurements yet to be finalized.

Figure 3. CEM test measurements in addition to the Base measurements listed in Figure 2.

Figure 4 summarizes key differences between PCIe 5.0 and PCIe 6.0. PCIe 6.0 PAM4 modulation enables the data rate to double while maintaining the same 16-GHz Nyquist frequency as PCIe 5.0. However, the channel budget has tightened, with the nominal channel loss going down from 36 dB for PCIe 5.0 to 32 dB for PCIe 6.0.

Figure 4. Key differences between PCIe 5.0 and PCIe 6.0.


Consequently, PCIe 6.0 requires improved equalization, achieved by increasing the continuous time linear equalizer (CTLE) to six poles with three zeros, compared to four poles with two zeros for PCIe 5.0, and it necessitates increasing the number of decision feedback equalization (DFE) taps from three to 16 to mitigate the chances of error seen at the receiver.

Figure 5 shows the variable DC gain of the 11 possible CTLE curves for PCIe 5.0 (left) and PCIe 6.0 (right). The 11 PCIe 6.0 CTLE curves are tighter around the peak compared with the PCIe 5.0 curves, and all the PCIe 6.0 curves peak around 4 dB, whereas the PCIe 5.0 curves peak around 1 dB.

Figure 5. CTLE curves for PCIe 5.0 (left) and PCIe 6.0 (right). Images from PCI Express Base Specification 6.0. Copyright 2022 PCI-SIG®.

Error Correction

Receiver reliability has improved in PCIe 6.0 with the introduction of forward error correction (FEC). In addition to FEC, the PCIe 6.0 specification also features cyclic redundancy check (CRC), as does PCIe 5.0. FEC operates on the principle of a transmitter sending redundant data that can be deployed to correct some errors at the receiver, while CRC is an error detection code used to detect the errors. For PCIe 6.0, each 256-byte flow-control unit (FLIT) comprises 242 bytes of payload, which are protected by eight bytes of CRC. The 250 bytes of payload and CRC combined are protected by six bytes of FEC.

A receiver uses the FEC to correct any errors in a FLIT, after which it applies the CRC check on the 250 bytes that are protected by the CRC. If a FLIT fails the CRC check, a PCIe 6.0 link-layer retry mechanism eventually sends the corrected data. PCIe 6.0 technology achieves low latency through a combination of relatively low BER rate of 1e-6 combined with a lightweight FEC to complete the initial correction.

PCIe Test Points

As mentioned, Base transmitter testing involves measuring a signal at a chip’s transmitter pin. Typically, the chip is soldered to a custom test board which breaks out the signals to physical connections to an oscilloscope’s input channels. For CEM testing, also known as compliance testing because it is performed to ensure interoperability, the signal is measured at the CEM connector for an add-in card or system board using compliance test fixtures purchased through the PCI-SIG website (Figure 6).

Figure 6. Base transmitter test at chip pin and CEM test at system board connector.

PCIe 6.0 Base Tx Jitter Measurements

A key measurement consideration for PCIe 6.0 is uncorrelated jitter, which represents timing margin that cannot be recovered through equalization. The jitter measurement methodology has five steps:

1. Acquire many repetitions of a known jitter-measurement pattern.

2. Look at the timing distribution of each individual edge in the pattern.

3. From that timing distribution extract the Gaussian component, RJ, and non-Gaussian component, UDJDD (the uncorrelated deterministic jitter derived using the Dual Dirac model).

4. Remove the oscilloscope noise contribution from RJ.

5. Aggregate the RJ and UDJDD for all edges and calculate uncorrelated total jitter (UTJ) for the entire signal.

The PCIe 6.0 Base specification defines the known jitter measurement pattern (Figure 7) used in step 1 above, and the measurement algorithm uses specific parts of the pattern for the jitter calculations. The pattern consists of a 52-UI repeating sequence consisting of four sets of 13 UIs, covering all 12 voltage-level transitions in the PAM4 signal. (Each set of 13 UIs includes a repeating symbol that is not used in the calculations.)

Figure 7. Known jitter-measurement pattern for PCIe 6.0.

The uncorrelated jitter is calculated from the timing distribution for each of the 12 voltage-level transitions in the pattern's 48 edge transitions. Figure 8 shows how noise impacts the amount of jitter present on each of the 12 transitions. A slow transition edge, such as a 0 to 1 edge, is more susceptible to jitter than a 0 to 3 transition, as shown by the histograms in Figure 8. The bottom right histogram represents a 0 to 1 edge that contributes about 2 ps of jitter. The histogram on the top right represents a 0 to 3 edge, which contributes about half the jitter compared to the 0 to 1 edge. In addition, oscilloscope noise (which must be removed from the jitter measurements) will impact the jitter observed on both the slow transitions and fast transitions.

Figure 8. Histograms showing jitter for a 0 to 3 edge (top) and 0 to 1 edge (bottom).

The Dual Dirac model can be used to extract the uncorrelated random jitter and deterministic jitter on each of the 48 edges individually. Figure 9 outlines the process, showing a probability distribution function (PDF) of one of the 40 edges in the jitter-measurement pattern. Q in the figure relates to the population of the statistics—more data captured on the oscilloscope translates to a higher statistics population.

Figure 9. Probability distribution function of one edge of the PCI 6.0 jitter-measurement pattern. Image from PCI Express Base Specification 6.0. Copyright 2022 PCI-SIG®.

1/RJ is a best-fit line to the Gaussian shape of the distribution function. Extending this line to Q=0 yields the deterministic jitter for one edge. The left-hand and right-hand 1/RJ lines intersect Q=0, and the difference between these two intersections equals the deterministic jitter. Extending the 1/RJ lines to intersect Q=7 yields the uncorrelated total jitter for one edge.

In summary, the process to measure and calculate the uncorrelated jitter component is:

1. Measure the 48 transitional edges on the jitter measurement pattern.

2. Analyze the PDFs of each of the 48 transitional edges, taking the average of each of these transitions.

3. Remove the oscilloscope noise contribution from the random jitter component.

4. Aggregate the random jitter and uncorrelated deterministic jitter for all edges and calculate the uncorrelated total jitter for the entire signal.

Teledyne LeCroy's SDAIII-PCIE6* oscilloscope software option automates the process of breaking down the jitter component into the 48 transitional edges, enabling you to make both individual and aggregated measurements. The table on the top left of Figure 10 shows measurements for some of the transitional edges, while the bottom shows the aggregated values.

Figure 10. Table of transitional edges (top left) and aggregated values (bottom).

Additional jitter measurements in the PCIe 6.0 Base specification are very similar to their PCIe 5.0 counterparts. The uncorrelated pulse-width jitter measurements for PCI 6.0 employ a high-swing toggle pattern alternating between 0 and 3. This pattern results in a two-voltage-level NRZ signal, for which you can use the same methodology as in PCIe 5.0 to calculate the pulse-width jitter.

*Note:The SDAIII-PCIE6 option extends the SDAIII or SDAIII-CompleteLinq Serial Data Analysis software. Working with PCIe 6.0 signals also requires the SDAIII-PAMx option for multi-level PAM signal support.